Low-Delay FPGA-Based Implementation of Finite Field Multipliers

Arithmetic operations over binary extension fields GF(2 m ) have many important applications in domains such as cryptography, code theory and digital signal processing. These must be fast, so low-delay implementations of arithmetic circuits are required. Among operations, field multiplication is considered the most one. For hardware implementation finite fields, irreducible trinomials pentanomials normally used. In this brief, FPGA-based bit-parallel polynomial basis multipliers presented, where a new multiplier based on given. Several post-place route results Xilinx Artix-7 FPGA for different reported. Experimental show that proposed exhibits best delay, with delay improvement up to 4.7%, second Area×Time complexities when compared similar found literature.